• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A system for transmission and display of texts on a television screen enables a display of a magazine made up of several pages. The packets of data relative to one page are transmitted without being multiplexed with the packets from another page of the same magazine. The data of one page begins with a page flag which is followed by data indicating the number of the page and ends with the flag of the following page. The data from each page is grouped in rows, preceded by a row flag. Each page contains an order row of the data which is operation data and is not used for display. Certain pages contain only the data which is relative to the shape of characters of the alphabet and the pages are not for display. They include in their order rows a specific operation octet which is recognized in the receiver. Responsive to this page, the system switches the subsequent data from the alphabet page towards the writing circuit of one of many shape memories, in order to record there the character shape data.
    公开号:SU1012809A3
    申请号:SU792736349
    申请日:1979-03-07
    公开日:1983-04-15
    发明作者:Брюск Роже；Марти Бернар；Пуанье Ален；Савари Жан-Ив
    申请人:Этаблиссман Пюблик Де Диффюзьон Ди "Теледиффюзьон Де Франс" (Фирма)；
    IPC主号:
    专利说明:

    the output of the second delay register and the second decoder input are the inverter, the seventh and eighth And elements, the fourth delay register, the ninth And element and the first decoder, are in series connected to the output of the second element And the fifth delay register, the tenth And element, and the second decoder, outputs which is connected to the corresponding control inputs of the fourth memory of the character generator, a buffer memory element has been entered, the input of which is connected to the output of the control panel, and the output is connected to the second input of the second element This comparison, introduced the sixth delay register, connected between the output of the first comparison element and the first input of the first element, introduced the second memory register, the output of which is connected to the second input of the third comparison element, introduced the third memory register, the output of which is connected to the first input of the fourth the comparison element, the fourth memory register is entered, the output of which is connected to the second input of the fifth AND element, and the eleventh AND element is entered, the first input of which is connected to the output of the second comparison element , the second is connected to the inverter output, and the output is connected to the second input of the fourth And element, while the first input of the first comparison element is connected to the second inputs of the first, third, sixth, eighth, tenth And elements, the second delay register, the fifth comparison element and with the third input of the third reference element, the first output of the second delay register is connected to the second input of the seventh And element, the second output to the second input of the second And element, and the third output to the control input of the decoder. .
    one
    The invention relates to television technology and can be used in Teletext systems for displaying additional textual and graphical information on television receivers.
    A device for reproducing text and graphic characters on a CRT screen is known, comprising a video signal demodulator, a color signal decoder, a video signal switch and a cathode ray tube, and a selector and a data decoder sequentially connected to the video signal decoder and the second signal switch input, the second input of which is connected to the control panel Jlj.
    In this device, the character set (alphabet) is limited, which limits the information capabilities of the entire system in which such a device is used,
    Closest to the present invention is a device for playing text and graphic characters on the screen of a cathode ray tube, which contains a memory unit that includes a serially connected first switch, a rewriter unit, a buffer drive 5, a first storage device and a second information storage device, the second input of which is connected to the first the output of the first switch, the second output of which is connected to the second input of the buffer accumulator, a character generator containing the first, second and third memory elements in passages which are connected respectively to the inputs of the first, second and third shift registers, and the inputs are combined and connected to the output of the second accumulator block information memory mixer and clock generator, wherein the outputs of the first,
    The second and third shift registers are connected via the second switch to the first input of the mixer, the control input of the switch, the combined control inputs of the shift registers, the second, third, fourth, and fifth inputs of the mixer, and the sixth input through the single-vibrator connected to the corresponding 3. 1 outputs of the first storage unit of the memory unit, a data decoder, comprising the first comparison element, the first input of which is the information signal input, and the first memory register, the output of which is connected to the second input of the first comparison element, and the control panel 2. In practice, in such a device, each element of the character generator memory contains the characters of an alphabet. Consequently, the number of alphabets used in the Teletext service may be more than two or three. However, it is not possible to increase the number of memory elements in the character generator due to an increase in equipment cost. Thus, the disadvantage of this device is also the limited number of displayed characters on the CRT screen. On the other hand, there are variants of alphabets. Thus, for example, the Latin alphabet in all its variants with sax pant letters, numbers and punctuation marks has more than 200 different signs. The Cyrillic alphabet, with its own national variants, the Azerbaijani and Uzbek alphabets, requires about 50 additional characters. In the Greek alphabet, there are about fifty different forms, the Arabic alphabet contains 28 letters, each of which can have four different Forms, depending on whether it is placed at the beginning, at the end, or in the middle of a word, or is used alone. The aim of the invention is to increase the number of reproducible text and graphic characters. To achieve this goal, a text and graphic character playback device on the screen of a cathode ray tube containing a memory unit comprising a first switch connected in series, a rewrite unit, a buffer storage device, a first information storage device and a second information storage device, the second input of which is connected to the first output of the first switch , the second output of which is connected to the second input of the buffer accumulator, a character generator containing the first, second and third memory elements, whose inputs are The inputs are respectively connected to the inputs of the first, second, and third shift registers, and the inputs are combined and connected to the output of the second storage unit of the memory unit, a mixer, and a clock generator, with the outputs of the first, second, and third shift registers being connected to the first through the second switch. the input of the mixer, the control input of the switch, the combined control of the shift registers in the second, third, fourth, and fifth inputs of the mixer directly, and the sixth input through the single vibrator is connected to the corresponding The first outputs of the first storage unit of the memory unit, the data decoder including the first comparison element, the first input of which is the information signal input, and the first memory register, the output of which is connected to the second input of the first comparison element, and the control panel, are entered into the character generator between the input of the first memory element and the fourth input of the switch, the successively connected fourth memory element and even the shift register, the control input of which is connected to the control input of the first about the shift register, and the first AND element, the first delay register, the second element compared, the third comparison element, the second delay register, the second And element, the third And element, the third delay register, the fourth Comparison element, the fourth And, Fifth And, Fifth. Comparison Element, Sixth And And Decoder, the first and second outputs of which are connected respectively to the input of the first switch and the first input of the second storage unit of the memory unit, are entered The inverter, the seventh and eighth And elements, the fourth delay register, the ninth And element, and the first decoder, are connected in series between the second output of the second delay register and the second decoder input, and the first decoder are sequentially connected to the output of the second element And the fifth register of the 9th, the tenth element VI and the second decoder, which are connected to the corresponding control inputs of the fourth memory element of the character generator, are entered into a boolean memory element, the input of which is connected to the output of the control panel and the output is connected to the second input of the second comparison element is entered; the sixth delay register is inserted. included between the output of the first comparison element and the first input of the first element I, the second memory register is entered, the output of which is connected to the second input of the third comparison element, the third memory register is entered, the output of which is connected To the first input of the fourth comparison element, a fourth memory register is entered, the output of which is connected to the second input of the fifth And element, and also the eleventh And element is entered, the first input of which is connected to the second output the second comparison element, the second with the inverter output, and the output is connected to the second input of the fourth AND element, while the first input of the first comparison element is connected to the second inputs of the first, third, sixth, eighth and tenth AND elements, the second delay register, n the first output of the second delay register is connected to the second input of the seventh And element, the second output to the second input of the second And element, and the third output to the control input of the decoder. FIG. Figure 1 shows the structural electrical circuit of the device for reproducing text and graphic characters on the screen of a cathode ray tube; in fig. 2 is a structural electrical circuit diagram of the memory block and the character generator; in fig. 3 structural electrical data decoder circuit; in fig. - forms reproducible, signs. A device for reproducing textual and graphic characters on a screen of a cathode ray tube, contains a video demodulator 1, a color signal decoder 2, a video signal switch 3, a cathode ray tube (, SLT), a separator of signal and text data 5, a selector 6, a transition unit 7, data decoder 8, memory unit 9 in character generator and control unit 11. Data sender 8 contains first, second, third, fourth and fifth elements of comparison 12-16, first, second, third and fourth. memory registers ty 17-2P, first, second, third, fourth, fifth, sixth, seventh. the eighth, ninth, tenth and eleventh elements And 21-31, first, second, third, fourth, fifth and sixth delay registers 32-37, first and second decoders 38 and 39, decoder 0, inverter il and buffer element memory 2. The memory block 9 contains the first switch 3, the rewriter block 4, the buffer drive kS, the first and second drives of information kf} and +7. Character generator 10 contains first, second, third, and fourth memories 48-51, first, second, third, and fourth shift registers 52-55, mixer 5b, clock generator 57, second switch 5B, and one-shot 59 Text and graphic playback device marks on the CRT screen works as follows. The video demodulator 1 divides the signal received by the television receiver to an audio and full television video signal, which is fed to the decoder of the color signals 2 and to the divider of the video signal and text data 5. The text data signal in the eight-bit parallel code is fed through the selector 6 and the transition block 7 to the data decoder 8. Information is exchanged between these blocks in eight-bit binary words (octets). The operation of the decoder data 8 can be seen on the example of those messages transmitted by the teletext system that contain alphabet characters recorded in the fourth memory element 51 of the character generator 10. In the teletext system, such a message is transmitted as a usual memory block page containing the totality for recording any data alphabet. Such a page may look as follows: PAGE 2 1 4 LINE ABOUT ABOUT ROOOOO R1100, 1, 5 RETURN OF THE CARRIAGE DL E STRING A ABOUT QOOOII Q10000 1 Q00100 AUTOC 2 QOIOOO QOOIOO ... 6 Q01000 Q00100 7 QOOOOO QOOOOO ... 9 QOOOOO QOOOOO E STRING In O ... PAGE ... In this message, each octet is enclosed between two characters. Octet PAGE indicates the page pointer. A single digit in the octet indicates the numerical value of the octet in decimal place. The octet LINE denotes a string pointer. The letter P, followed by binary digits 1, and O indicates elements from the binary elements of the octet, allowing detection and correction of transmission errors, while the following binary elements are useful data. The octet RETURN of the CARRIAGE indicates the end of service data. A DLE octet if it is followed by an octet. A LINE indicates that the data that follows further to the next DLE combination is a character of the alphabet. A single letter in the octet indicates the address of the unitary matrix in the fourth memory element 51, by which the character should be written. In this example, to simplify the description, each letter refers to the Latin alphabet stored in the first second and third memory elements kS, kS, and 50. The letter Q, followed by five binary digits, plays the same role as the letter P, whereas binary elements 1 indicate the position of black dots in each row of the matrix. In the matrix depicted in FIG. k and containing the letter A, i.e. The first letter, the composition of which is transmitted in the described message, each line is described by fle with twe bits (binary characters). Suppose that in the message these ten bits are divided into two parts of five bits, which together with the bits O form, form two successive octets. After the octet, the letter A is followed by the octet O, indicating that the two octets following it describe the row O of the matrix shown in FIG. a, then the octet 1 follows, indicating that the two octets following it describe line 1, and so on. For lines 7-9, the line octets contain only zeros. Therefore, descriptions of these blank lines are not transmitted. Of course, if the octet of the description of the lines corresponds to octet 01E during the message, it is doubled in transmission to satisfy the technical standards.
    When in the first element of comparison. 12 enters, the octet PAGE in case of coincidence with the Contents of the first memory register 17 is launched
    the sixth delay register 37. The three following octets 7., 1, indicating the page number to be transmitted, are entered using the first element 21 and the first delay register 32 and then in the second element 13 are compared with the contents of the buffer memory element k2 containing the number In the case of a match to the subscriber of the page, if the match of the third element of comparison I is activated, the following octets are successively compared with the content of the second memory register 18, i.e. with octets "STRING O O and ROOOO. When a match occurs, it indicates that we are talking about the incoming service data of line O. On the other hand, the output of the second element of comparison 13 activates the first input of the eleventh element And 31. The octet P1100, at least, concerns its last four bits, comes from the second delay register 33. In the described example, the first and second outputs of the second delay register 33 are activated, which causes the eleventh element 31 to close using the inverter C, but the second element 22 opens, which, in turn, covers the third element And 23. Thus, the eleventh element And 31 through the fourth and fifth elements And 2 and 25 and the fifth element of comparison 16 closes the sixth element And 26, which means that the page will not be visually displayed. In this case, a signal from the fourth register of memory 20, containing the OKRET RETURN octet, is sent to the second input of the second element I 25.
    This page has the following structure: PAGE 3 8 LINE О О РООПО Р0100 О 1 RETURN OF THE CARRIAGE LINE 1.1 iup uQi. E2 CAR CAR CAR .. PAGE ...
    If the subscriber dialed a number on the control panel 11, then the operation of the data decoder 8 is similar to the described operation until it arrives in the second delay register 33 octets of P0100. In this case, the second output of the second delay register 33 is not activated, so that the eleventh AND 31 opens the first output of the second delay register 33, which causes the seventh And 27 element to open instead of the second And 22 element, and the seventh And 27 element opens the eighth And element 28 and the fourth delay register 35 post the next two octets indicating the alphabet 01. Comparison is made with the content of the third memory register 13, the fourth element of the comparison 15 states the agreement with tr m recorded values and opens the fourth element And 2, the second input of which is connected to the eleventh element And 31. The fifth element And 25 is open, and when the fifth element is compared, 16 from the information signal input of the data decoder 8 octets BOvSBPAT CARRIDES opens the sixth element And 2b, thanks to which the remaining part of the page goes to the decoder tO. On the other hand, the output of the fourth element of comparison 15 is also connected to the second input of the ninth element I 29, the first input of which is connected to the output of the fourth delay register 35, and from the output of the ninth element I 29 and the first decoder ZV receives the al-favit number written in to the fourth register of the delay 35. In the described case, the first decoder 3B transmits this number without changing to the second input of the encoder iO. From the output of the decoder k, the number enters the first storage unit f of memory block 9. On the other hand, the third element AND 23 in the open state ensures the introduction of the next two octets 1 and 5 into the third delay register, where they indicate that the The alphabet has number 15 in the particular case of the described example. On the other hand, after a delay of two octets in the fifth delay register B, the tenth element I 3 passes the remaining part of the message to the second decoder 39 until a new page pointer arrives in the first element of comparison 12, in this case the output of the first element 12 compares (all elements of data decoder 8 are stored with the exception of the buffer memory element and the third delay register Z) to their initial state. The receipt of a 39 octet into the second decoder of the RETURN OF THE CARRIAGE triggers it. After receipt and recognition For each OLE LINE combination, the next octet of the character determines the address of the unitary matrix of the fourth memory element 5, into which the next character form is written, and then the next octet of the line defines the matrix line, into which the bit of the first form is written. or the third memory element is +8, 49, or 50, then the decoder P detects, t octets of the line pointer and decodes two octets that follow each octet to subtract the line number from them, which is transmitted to memory block 9 for In order to serve as the address in the first 6 and second accumulators of information 7, while the other octets of each row are transmitted to the first switch A3, the data coming to the input of the first switch 3 can be combined into the following groups: first of all, in the simplest case, the octet alphanumeric characters., then a classic octet of operations and, finally, an octet of separation, plus an octet of identity of the model of the character. The first switch k3 contains the means allowing to detect data of the third group - separation octet plus octet of the model's identity. {These tools can be simple comparing devices) and send them to the input of the kk rewrite unit 5, which detects the recording of octets of characters in the second storage device 7 and manages the rewriting at the same address as the addresses of the octets of the characters of the preceding octets of the model's identity from the buffer accumulator 5 to the first storage device 6. The rewriting takes place without ichtozheni content buffer accumulator 5. Depicted in FIG. 2, the generator 10 characters contains four memory elements 48-51, three of which are classical memory elements 48, 49, and 50, and the fourth memory element 51 is random access memory, the second switch 58, the mixer 5b, and the one-shot 59 Each of the memory elements 48-51 is connected to the corresponding shift register 52-55, whose role is to transform into a sequential series of binary elements read from the memory elements.
    in a classic way in parallel. The character form is scrolled in memory elements 8-51 line by line, and each line corresponds to a TV screen raster. Generator 57 controls reads from jS-Sl, depending on the horizontal sync signals.
    The readout pitch of the second information accumulator V7 is connected in parallel to the inputs of the read addresses of the memory elements 8-51, the parallel data outputs of which are respectively connected to the parallel inputs of the shift registers 52-55.
    The second switch 5B is designed to select one of the shift registers 52-55 for connecting its output to the mixer 5b, which is controlled from the first storage of information 6 of the memory block 9 through the one-shot 59.
    The fourth memory element 51 is RAM, which in the example being described is divided into Eons, into which binary elements corresponding to square matrices of 100 dots are inscribed, such as the matrices shown in FIG. 4. For example, the matrix shown in FIG. I also represent a capital Latin letter, contains ten lines, the first of which corresponds to the binary word 001110000, the second to the binary word 0010001000, etc., each word containing ten binary elements (bits).
    When using the matrix shown in FIG. , depicting a Latin lower-case letter, a series of ten words is easily distinguishable by ten bits, which must be written into the fourth element of the month t and 51, so that the latter can be used in the character generator 10.
    The matrix shown in FIG. c, by way of example, represents a lowercase letter from Cyrillic, and the matrix shown in FIG. shows the symbol used in railway and hotel services.
    It is assumed that the fourth memory element 51 can store 1.8 character forms, which can be sent to addresses, both for writing and reading in the help of word 7 of the bits defined by the address. Since each zone contains ten subzones of ten bits, it is necessary to provide one more word of j bits, defining the address of the subzone.
    The signals corresponding to the characters formed in the mixer 5b are fed to the second input of the video signal switch 3, where they are combined with the signals of the television image and fed to the CRT.
    Thus, the proposed device makes it possible to reproduce a large number of text and graphic characters on a CRT screen. Practically any signs can be reproduced (Formed from a matrix with the dimension of dots.
    J ,,.
    oh oh oh oh oh oh oh
    FI1. /
    .one
    Jj
    l j /
    a
    /five
    lH3r
    gk - T
    -S
    Jk
    -i
    J /
    Fig.Z
    权利要求:
    Claims (1)
    [1]
    DEVICE FOR PLAYING TEXT AND GRAPHIC SIGNS ON THE ELECTRON BEAM TUBE (CRT) SCREEN, comprising a memory unit including a first switch in series, an overwrite unit, a buffer storage device, a first information storage device and a second information storage device, the second input of which is connected to the first output of the first output device the second output of which is connected to the second input of the buffer storage, a character generator containing the first, second and third memory elements, the outputs of which are connected respectively to the moves of the first, second and third. shift registers, and the inputs are combined and connected to the output of the second storage device information of the memory unit, the mixer and the clock generator, and the outputs of the first, second and third shift registers through the second switch are connected to the first input of the mixer, the control input of the switch , the combined control inputs of the shift registers, the second, third, fourth and fifth inputs of the mixer directly, and the sixth input through a one-shot connected to the corresponding outputs of the first For information of a memory block, a data decoder including a first comparison element, the first input of which is an input of an information signal, and a first memory register, the output of which is connected to the second input of the first comparison element, and a control panel, characterized in that, in order to increase the number of reproducible text and graphic characters in the character generator is introduced between the input of the first memory element and a fourth input of the switch is connected in series-d nye fourth memory element and s fifth fourth shift register, y governing entrance. which is connected to the control input 'of the first shift register, and the first element AND, the first delay register, the second control element, the third comparison element, the second delay register, the second AND element, the third AND element, the third delay register, are introduced in series with the data decoder the fourth element of comparison, the fourth element of And, the fifth element of And, the fifth element of comparison, the sixth. an And element and a decoder, the first and second outputs of which are connected respectively to the input of the first switch and the first input of the second storage device of the information of the memory block, an inverter, the seventh and eighth elements of And, the fourth register are sequentially connected between the second output of the second delay register and the second input of the decoder delays, the ninth element And and the first decoder, introduced in series connected to the output of the second element And the fifth delay register, the tenth element And and the second decoder, the outputs of which are connected to the corresponding control inputs of the fourth element of the memory of the character generator, a buffer memory element is introduced, the input of which is connected to the output of the control panel, and the output is connected to the second input of the second comparison element, the sixth delay register is inserted, included between the output of the first comparison element and the first input of the first element And, . a second memory register is introduced, the output of which is connected to the second input of the third comparison element, a third memory register is introduced, the output of which is connected to the first input of the fourth comparison element, a fourth memory register is introduced, the output of which is connected to the second input of the fifth AND element, and also introduced the eleventh element And, the first input of which is connected to the output of the second comparison element, the second to the output of the inverter, and the output is connected to the second input of the fourth element And, while the first input of the first comparison element is connected with the second inputs of the first, third, sixth, eighth, tenth elements of Which delay register, fifth comparison element and with the third input of the third comparison element, the first output of the second delay register is connected to the second input of the seventh element And the second Output is to the second input of the second element And, and the third output is to the control input of the decoder. .
    类似技术:
    公开号 | 公开日 | 专利标题
    SU1012809A3|1983-04-15|Device for displaying textual and graphical characters on the screen of cathode ray tube
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    US3891792A|1975-06-24|Television character crawl display method and apparatus
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    US4604712A|1986-08-05|Apparatus for controlling reproduction of text characters whose form depends on adjacency of other characters
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    US4323892A|1982-04-06|Alpha-numeric character generator arrangement
    US3582936A|1971-06-01|System for storing data and thereafter continuously converting stored data to video signals for display
    US4933764A|1990-06-12|Improved teletext decoder which accommodates an increased number of character codes
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    CA1078525A|1980-05-27|Data stores and data storage system
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    US3918040A|1975-11-04|Circuit for the raster writing conversion of data to be reproduced on a video screen
    KR0180739B1|1999-05-01|Ideographic teletext transmissions
    US4910595A|1990-03-20|Teletext decoders
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    EP0351912A1|1990-01-24|Teletext decoders
    US3699565A|1972-10-17|Video generator
    GB2051527A|1981-01-14|Method and apparatus for transmission of non-alpha numeric characters to a television receiver
    GB1593423A|1981-07-15|Digital transmission system
    同族专利:
    公开号 | 公开日
    DE2909873A1|1979-09-20|
    BE877606A|1979-11-05|
    JPS54126429A|1979-10-01|
    FR2419623A1|1979-10-05|
    NL188614B|1992-03-02|
    FR2419623B1|1981-12-04|
    JPH0124395B2|1989-05-11|
    CA1147845A|1983-06-07|
    NL188614C|1992-08-03|
    GB2022378B|1982-08-11|
    DE2909873C2|1987-11-12|
    US4290062A|1981-09-15|
    NL7901896A|1979-09-12|
    GB2022378A|1979-12-12|
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    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    FR7807551A|FR2419623B1|1978-03-10|1978-03-10|
    BE0/196227A|BE877606A|1978-03-10|1979-07-10|DIGITAL TRANSMISSION SYSTEM FOR DISPLAYING TEXTS AND GRAPHICS ON A TELEVISION SCREEN|
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